Generally, the sense amplifier circuitry installed within a CMOS DRAM device for sensing data from the cell comprises a sensing clock driver, a restoring clock driver, a delay means and a sense amplifier. Sensing clock signals for sensing the data from the cell and restoring clock signals for restoring the data into the cell cause an increase in the peak current if they have steep slope characteristics during transitions from a high level to a low level, or vice versa. In such a case, noise will be generated, and malfunctions can be induced. According to the conventional solutions for this problem, steep slopes generated during transitions of sensing clock signals or restoring clock signals are divided into double or multiple steps in order to obtain gentle slopes. The conventional sense amplifier driver circuit having multi-slope characteristics and referred to in this application is illustrated in FIG. 1.
However, in the circuits according to conventional technologies, despite the above-mentioned advantages, the MOS transistors within the sensing clock driver are simultaneously turned on during a short period of time to form a DC current path, thereby consuming DC current. This is so due to the fact that, when the precharge operation for the sense amplifier is started upon termination of the sensing and restoring operation, delayings of the trailing edges of the sensing clock signals and restoring clock signals occur based on the multi-slope characteristics of the sensing clock driver and restoring clock driver. The MOS transistors within the restoring clock driver will also form a DC current path together with a part of the sense amplifier, thereby dissipating DC currents also. This will cause a large dynamic power loss in the whole high density memory device.